1. Field
The present disclosure generally relates to the design of chip packages. More specifically, the present disclosure relates to a chip package that includes a group of semiconductor dies arranged in a plank stack and a substrate oriented at a right angle relative to the plank stack, and which communicates with the semiconductor dies.
2. Related Art
Chip packages that include stacked semiconductor chips can provide significantly higher performance in comparison to conventional individually packaged chips that are connected to a printed circuit board. These chip packages also provide certain advantages, such as the ability: to use different processes to fabricate different chips in the stack, to combine higher density logic and memory, and to transfer data using less power. For example, a stack of chips that implements a dynamic random access memory (DRAM) can use a high metal-layer-count, high-performance logic process in a base chip to implement input/output (I/O) and controller functions, and a set of lower metal-layer-count, DRAM-specialized processed chips can be used for the rest of the stack. In this way, the combined set of chips may have better performance and lower cost than: a single chip that includes the I/O and controller functions manufactured using the DRAM process; a single chip that includes memory circuits manufactured using a logic process; or a system constructed by attempting to use a single process to make both logic and memory physical structures.
It can, however, be difficult to obtain low-cost, high-performance (e.g., high-bandwidth) interconnections between the stacked chips. For example, the chips can be electrically coupled using wire bonds between exposed bond pads on surfaces in a stack of chips in which the chips are offset from one another to define a staircase of chip edges. But while these wire bonds can be implemented using low-cost assembly techniques, the resulting wire bonds typically have a low bandwidth.
In contrast, TSVs typically have a higher bandwidth than wire bonds. In a TSV fabrication technique, chips are processed so that one or more of the metal layers on their active face are conductively connected to new pads on their back face. Then, chips are adhesively connected in a stack, so that the new pads on the back face of one chip make conductive contact with corresponding pads on the active face of an adjacent chip.
However, TSVs typically have a higher cost than wire bonds. This is because TSVs pass through the active silicon layer of a chip. As a consequence, a TSV occupies area that could have been used for transistors or wiring. This opportunity cost can be large. For example, if the TSV exclusion or keep-out diameter is 20 μm, and TSVs are placed on a 30-μm pitch, then approximately 45% of the silicon area is consumed by the TSVs. This roughly doubles the cost per area for any circuits in the chips in the stack. (In fact, the overhead is likely to be even larger because circuits are typically spread out to accommodate TSVs, which wastes more area.) Furthermore, fabricating TSVs usually entails additional processing operations and yield loss, which also increase cost. In addition, TSVs typically limit the number of stacked semiconductor dies and usually present a significant challenge for thermal management when a large number of semiconductor dies are stacked.
Hence, what is needed is a chip package that offers the advantages of stacked semiconductor dies without the problems described above.